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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-28500-5E
ASSP
AD/DA CONVERTER
MB40166/MB40176
1-CHANNEL 6-BIT AD/DA CONVERTER WITH CLAMP CIRCUIT
The Fujitsu MB40166 and MB40176 are low power 6-bit AD/DA converter which is fabricated with Fujitsu Advanced Bipolar Technology. MB40166 and MB40176 have the same basic circuits and functions, with the only difference being that MB40166 has an independent analog input terminal for the A/D section and a clamp voltage output terminal, while MB40176 has an analog input in the A/D section internally connected with the clamp circuit. Since both models contain a single-chip clamp circuit and a reference voltage circuit, they are ideal for video signal processing.
* * * * * * * * *
Resolution Linearity Error Maximum Conversion Rate Analog Input Voltage Range 0 to 1.0 V (MB40176) Analog Output Voltage Range Digital I/O Level Power Supply Voltage Power Dissipation:300 mW typ. Package
28pin Plastic FLAT Package 28pin Plastic DIP Package
:6 bits :0.8% max. :20 MSPS min. :VREF to VCCA (MB40166) :VCC to VCC -1 V :TTL Level :+5 V
PLASTIC PACKAGE FPT-28P-M01
(Suffix : -PF) (Suffix : -P)
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating Power Supply Voltage Digital Input Voltage Analog Input Voltage Storage Temperature Symbol VCCA, VCCD VIND VINA TSTG Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCCA +0.5 -55 to +125 Unit V V V C
PLASTIC PACKAGE DIP-28P-M03
NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
1
MB40166/MB40176
s
PIN ASSIGNMENT
(TOP VIEW)
DACK
(MSB)
(TOP VIEW)
28 27 26 25 24 23 D.GND VCCD A.GND VCCA VOUT COMP VREF VINA VCLMP (N.C.) VCCA A.GND VCCD D.GND
(MSB) (LSB) (LSB) (MSB)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
MB40166
DACK DD1 DD2 DD3 DD4 DD5 DD6 DA6 DA5 DA4 DA3 DA2 DA1 ADCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
MB40176
28 27 26 25 24 23 22 21 20 19 18 17 16 15
D.GND VCCD A.GND VCCA VOUT COMP VREF C2 C1 VIN VCCA A.GND VCCD D.GND
DD1 DD2 DD3 DD4 DD5
(LSB) (LSB)
DD6 DA6 DA5 DA4 DA3 DA2
22 21 20 19 18 17 16 15
(MSB)
DA1 ADCK
(FPT-28P-M01) (DIP-28P-M03)
(FPT-28P-M01) (DIP-28P-M03)
Note : The functions of the terminals within the dotted lines above are different for MB40166 and MB40176.
2
MB40166/MB40176
s
BLOCK DIAGRAM
* MB40166
0.8VCCA VCLMP
20
CLAMP
REFERENCE VOLTAGE GENERATOR
VINA
21
ADCK
14
VCCA 0.8VCCA R1 1
13
0.8VCCA (MSB) DA1 DA2
R 2
63 to 6 ENCODER
LATCH & BUFFER
12
11
DA3
R 62
10
DA4
9
DA5 DA6 (LSB)
8
R
63
R2 VREF
22
DACK DD1 (MSB) to DD6 (LSB)
1
2
6
6
7
MASTER SLAVE REGISTER
6
BUFFER
6
CURRENT SWITCH
6
R-2R RESISTOR NETWORK
24
VOUT
15
28
17
26
16
27
18
25
23
D.GND
A.GND
VCCD
VCCA
COMP
Note : The circuits within the dotted lines above are different for MB40166 and MB40176.
3
MB40166/MB40176
s
BLOCK DIAGRAM (Continued)
* MB40176
VIN C1 C2
19 20 21
0.8VCCA CLAMP
REFERENCE VOLTAGE GENERATOR
ADCK
14
VCCA 0.8VCCA R1 1
13
0.8VCCA (MSB) DA1 DA2
R 2
63 to 6 ENCODER
LATCH & BUFFER
12
11
DA3
R 62
10
DA4 DA5
9
8
R
DA6 (LSB)
63
R2 VREF
22
DACK DD1 (MSB) to DD6 (LSB)
1
2
6
6
7
MASTER SLAVE REGISTER
6
BUFFER
6
CURRENT SWITCH
6
R-2R RESISTOR NETWORK
24
VOUT
15
28
17
26
16
27
18
25
23
D.GND
A.GND
VCCD
VCCA
COMP
Note : The circuits within the dotted lines above are different for MB40166 and MB40176.
4
MB40166/MB40176
s
PIN DESCRIPTIONS
Section Pin No. 40166 21 - 22 A/D 8 to 13 20 - - 14 24 2 to 7 D/A 23 1 18, 25 16, 27 17, 26 15, 28 Other 19 - - 20 21 40176 - 19 Symbol VINA VIN VREF DA1 to DA6 VCLMP C1 C2 ADCK VOUT DD1 to DD6 COMP DACK VCCA VCCD A.GND D.GND (N.C.) I/O I I O O O - - I O I - I - - - - - Analog signal input. Reference voltage output. Reference voltage divided by the resistors, with the output voltage set to 0.8 x VCCA (V). Digital signal outputs. (DA1: MSB, DA6: LSB) Clamp voltage output. Clamp capacitor is connected between these pins. A/D conversion clock input. Analog signal output. Digital signal input. (DD1: MSB, DD6: LSB) Phase compensation capacitor is connected. Insert a capacitor of 1 F or more between this pin and A.GND. D/A conversion clock input. Power supply for analog circuit. (+5 V) Power supply for digital circuit. (+5 V) Ground for analog circuit. (0 V) Ground for digital circuit. (0 V) No connection. Function
Common
5
MB40166/MB40176
s
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VCCA, VCCD VINA VIN VIHD VILD fCLK tW
+
Value Min 4.75 VREF 0 2.0 - - 20 20 12.5 7.5 1.0 1.0 1.0 0 Typ 5.00 - - - - - - - - - - - - - 0.8 20 - - - - - - - 70 Max 5.25 VCCA 1
Unit V V V V V MHz ns ns ns ns F F F C
Remarks
Power Supply Voltage Analog Input Voltage Digital High-level Input Voltage Digital Low-level Input Voltage Clock Frequency Clock Pulse Width at High Level Clock Pulse Width at Low Level Set-up Time Hold Time Phase Compensation Capacitance Clamp Capacitance Reference Voltage Capacitance Operating Temperature s
MB40166 MB40176
tWtS tH CCOMP CCLAMP CVREF Ta
ELECTRICAL CHARACTERISTICS
(VCCA=VCCD=5V5%, Ta=0 to 70C)
Parameter Symbol Condition Value Min Typ Max Unit Remarks
ANALOG CIRCUIT DC CHARACTERISTICS
Resolution Linearity Error Analog High Level Input Current Analog Low Level Input Current Equivalent resistance for Analog Input Analog Input Current Reference Voltage Clamp Voltage Full-Scale Output Voltage Zero-Scale Output Voltage Output Resistance Power Supply Current
Note : *VCCA=VCCD=5.0V
- LE IIHA IILA RINA IIN VREF* VCLMP VOFS VOZS RO ICC DC VINA = VCCA VINA = VREF VCCA - VREF IIHA - IILA
- - - - 400 -400 3.9 - - - - -
- - 8.5 7.5 - - 4.0 VREF VCCA VREF 240 60*
6 0.8 25 23 - - 4.1 - - - - 90
Bits % A A k A V V V V mA MB40166 MB40166 MB40166 MB40176
6
MB40166/MB40176
s
ELECTRICAL CHARACTERISTICS (Continued)
(VCCA=VCCD=5V5%, Ta=0C to 70C)
Parameter Symbol Condition Value Min Typ Max Unit
DIGITAL CIRCUIT DC CHARACTERISTICS
Digital High-level Output Voltage Digital Low-level Output Voltage Digital High-level Input Voltage Digital Low-level Input Voltage Digital High-level Input Current Digital Low-level Input Current
VOHD VOLD VIHD VILD IIHD IILD
IOH=-400 A IOL=1.6mA
2.7 - 2.0 - - -100
- - - - - -
- 0.4 - 0.8 20 -
V V V V A A
SWITCHING CHARACTERISTICS (VCCA=VCCD=5V5%, Ta=0C to 70C)
Parameter Symbol Condition Value Min Typ Max Unit
Maximum Conversion Rate Digital Output Delay Time Analog Output Delay Time Analog Output Rise Time Analog Output Fall Time
FS tPDD tPDA tr tf
20 8 - - -
- 15 13 15 15
- 30 - - -
MSPS ns ns ns ns
7
MB40166/MB40176
s
TIMING CHART
1. Timing Chart for A/D Conversion
tW+ tW3V 1.5 V A/D conversion clock input (ADCK) 0V
Analog signal input (VIN)
Sample N
Sample N+1
Sample N+2
tpdD VOHD Digital signal output (DA1 to DA6) 1.5 V DATA N-1 DATA N DATA N+1 VOLD
2. Timing Chart for D/A Conversion
tS th 3V Digital signal input (DD1 to DD6) 1.5 V 0V tW+ tW3V D/A conversion clock input (DACK) tr 90% 50% 10% tPLHA 90% 50% 10% tPHLA tf VOFS 1.5 V 0V
Analog signal output (VOUT)
VOZS
8
MB40166/MB40176
s
A/D CONVERSION CHARACTERISTICS
Ideal conversion characteristics (1LSB=16 mV)
STEP OUTPUT CODE , 63 111111 62 111110 61 111101
Actual conversion characteristics
STEP OUTPUT CODE , 63 111111 62 111110 61 111101 LE61
33 100001 32 100000 31 011111
33 100001 32 100000 LE31 31 011111 LE33 LE32
02 000010 01 000001 00 000000 4.000 V
02 000010 LE2 01 000001 00 000000 LE1 VZT LEn max FS
=
VINA, VIN
4.992 V
VINA, VIN Linearity Error
VFT
s
D/A CONVERSION CHARACTERISTICS
Ideal conversion characteristics (1LSB=16 mV)
A.OUT 5.000 V 4.984 V
Actual conversion characteristics
A.OUT VOFS LE62
4.520 V 4.504 V 4.488 V LE2 4.024 V 4.008 V 3.992 V LSB MSB VOZS 000000 000001 000010 000000 000001 000010 011111 100000 100001 111110 111111 011111 LE1 LE32
LE33
LE31
100000
100001
111110 62
31
32
33
62
63
31
32
33
Step
Step
63
Input Code
Input Code 0 1 2
0
1
2
111111
9
MB40166/MB40176
s
FUNCTIONAL DESCRIPTIONS CLAMP CIRCUIT
The clamp circuit contained in MB40166/MB40176 is a peak detector type, in which the top of the sync of the composite sync signal is clamped. Clamp voltage is common to the reference voltage (0.8 x VCC) of A/D and D/A circuits.
* MB40166 (1) Providing a clamp circuit
20
Clamp
VCLMP
-+
21
A/D
D/A
24
VOUT
A
VINA
8 13 2 7
(DA6 to DA1)
(DD1 to DD6)
VCCA
VCCA
1V
VREF Given voltage Input level at A Input level at VINA pin
VREF Output level of Vout
(2) Directly feeding the signal at the VINA pin
VINA
21
A/D
D/A
24
VOUT
8
13
2
7
(DA6 to DA1)
(DD1 to DD6)
VCCA
VCCA
VREF Input level at VINA pin
VREF Output level of Vout
10
MB40166/MB40176
* MB40176
VIN C1 C2 +
19 20 21
CLAMP
A/D
D/A
24
VOUT
8
13
2
7
(DA6 to DA1)
(DD1 to DD6)
1V
VCCA
VCCA
A. GND Input level at VIN pin
VREF Input level of C2
VREF Output level of Vout
11
MB40166/MB40176
s
ANALOG INPUT EQUIVALENT CIRCUIT
* MB40166
VCCA
~100
0.8 x VCC + VBE ~
~ 400 k
x 63 Circuits A.GND
20 21
VCLMP Equivalent circuit of clamp circuit block
VINA ADC analog input equivalent circuit
* MB40176
VCCA 100 ~
~ 4 k
0.8 x VCC + VBE ~
VIN 19
400 k ~
x 63 Circuits A.GND
20
-
+
21
C1
C2 ADC analog input equivalent circuit
Equivalent circuit of clamp circuit block
12
MB40166/MB40176
s
DIGITAL INPUT EQUIVALENT CIRCUITS
* MB40166/MB40176
Digital input equivalent circuit of A/D converter block
VCCD 50 k 3.2 k 50 k
1.6 k
1.6 k
ADCK
VT~ 1.4 V
D.GND
Digital input equivalent circuit of D/A converter block
VCCD 50 k 50 k
DA1 to DA6 DACK D.GND
VT~ 1.4 V
13
MB40166/MB40176
s
TYPICAL CONNECTION EXAMPLE
* MB40166
VCC
VCCA VCLMP VINA VOUT MB40166
VCCD DA ADCK DACK DD 6 6 CONTROLLER MB87045 MEMORY MB81464
COMP
A.GND
D.GND
10 H + 3.3 F 0.33 F
18 25 16 27
10 H 0.33 F + 3.3 F
VCCA Clamp voltage output Video signal ADC input Video signal DAC output
20
VCCA
VCCD
VCCD ADCK (MSB) DA1 (LSB) DA6
14
VCLMP VINA N.C. VOUT VREF COMP MB40166
ADC clock
21
13
19
8
ADC digital outputs (to controller)
24
(LSB) DD6 (MSB) DD1 DACK
7
22
DAC digital inputs (from controller)
2
23
1
DAC clock
1 F
+ -
+ 1 F -
A.GND
17
A.GND
26
D.GND
15
D.GND
28
Note : If the clamp circuit is used, connect VINA with VCLMP. If the clamp circuit is not used, do not connect VINA with VCLMP.
14
MB40166/MB40176
s
TYPICAL CONNECTION EXAMPLE (continued)
(1) Internal clamp circuit is used.
+9 V External component 2.2 k Analog input pin 2SA933 +
20
+5 V
+5 V
VCCA VCLMP 1 F
21
VCCD
MB40166 VINA A.GND D.GND
(2)Internal clamp circuit is not used.
+5 V
+5 V
VCCA OPEN
20
VCCD
VCLMP MB40166
Analog input pin *
21
VINA A.GND D.GND
*: Input voltage range for the analog input pin is VREF up to VCCA.
15
MB40166/MB40176
s
TYPICAL CONNECTION EXAMPLE (continued)
* MB40176
VCC
VCCA VIN C1 MB40176 C2 VOUT COMP A.GND
VCCD 6 DA ADCK DACK DD 6 D.GND CONTROLLER MB87045 MEMORY MB81464
10 F 3.3 F + 0.33 F
18 25 16 27
10 F 0.33 F + 3.3 F
VCCA Video signal ADC input 1 F + Video signal DAC output 19
VCCA
VCCD
VCCD ADCK
14
VIN C1 C2 MB40176 VOUT VREF COMP A.GND
17
ADC clock ADC digital outputs (to controller)
20
(MSB) DA1 (LSB) DA6 (LSB) DD6 (MSB) DD1 DACK
13
21
8
24
7
DAC digital inputs (from controller)
22
2
23
1
DAC clock
1 F
+ -
+ 1 F -
A.GND
26
D.GND
15
D.GND
28
16
MB40166/MB40176
s
TYPICAL CONNECTION EXAMPLE (continued)
1.ON-CHIP Input PNP Transistor is utilized.
+5 V
+5 V
VCCA Video signal input
19
VCCD
VIN
20
1 F +
21
-
C1
MB40176
C2 A.GND D.GND
Note : Input impedance of VIN input pin (19) is about 20 k, please pay attention to output impedance of signal source.
2. Input PNP Transistor of Clamp Circuit is put externally.
+9 V External circuit
+5 V
+5 V
VCCA 2.2 k + 1 F Video signal input 2SA933 A.GND
21
VCCD
C2
D.GND
Note : Both VIN (19) and C (20) are connected with VCCA.
17
MB40166/MB40176
28-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-28P-M01)
.110(2.80) MAX +.010 +0.25 .699-.008 (17.75 -0.20 ) (MOUNTING HEIGHT) .002(0.05) MIN (STAND OFF HEIGHT)
.402.016 (10.200.40) INDEX .299.012 (7.600.30) .362.012 (9.200.30)
.020.008 (0.500.20) .050(1.27) TYP .018.004 (0.450.10) .005(0.13)
M
+.002 +0.05 .006-.001 (0.15 -0.02 ) Details of "A" part
"A"
.008(0.20)
.004(0.10) .650(16.51) REF
.024(0.60) .007(0.18) MAX .027(0.68) MAX Dimensions in inches (millimeters)
(c)1994 FUJITSU LIMITED F28005S-5C
18
MB40166/MB40176
28-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-28P-M03)
15MAX
INDEX-1 .358.010 (9.100.25) .400(10.16) TYP
INDEX-2 +.008 +0.20 1.024 -.012 (26.00 -0.30 ) .070(1.778)MAX .010.002 (0.250.05)
.191(4.85)MAX
.118(3.00)MIN .070.007 (1.7780.18) +.020 .039 -0 (1.00 +0.50 ) -0
.018.004 (0.450.10) .910(23.114)REF
.020(0.51)MIN
(c)1994 FUJITSU LIMITED D28012S-3C
Dimensions in inches (millimeters)
19
MB40166/MB40176
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 1015, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609
All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
F9601 (c) FUJITSU LIMITED Printed in Japan
20

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